As a spin-off from my blog, I'm collecting some posts that are related to FPGA and a few other topics on this website. Currently, these are the pages published here:
- Techniques for logic design
- Crossing clock domains
- Clock domains, related clocks and unrelated clocks
- Metastability and the basics of clock domain crossing
- Clock domain crossing with data
- Initializing an FPGA and resets
- Asynchronous resets on FPGA: Not as easy as many believe
- Resets on FPGA: Synchronous, asynchronous or not at all?
- The logic for starting off and resetting an FPGA properly
- Arithmetics in Verilog
- Using IP in the design
- Constraints and controlling the design tools
- Timing and timing constraints
- Timing is everything
- The fundamentals of timing in logic design
- The clock period constraint and its timing analysis
- More about the clock period constraint
- The art of Timing Closure
- Strategies for timing closure
- The clock period constraint, and clock objects
- Using Tcl commands to select logic elements
- Timing exceptions
- Timing constraints and clock domain crossing
- Timing constraints for multi-cycle paths
- Choosing the strategy for I/O timing
- I/O timing constraints in SDC syntax
- Validating that the timing constraints are correct
- Using wildcards and -hierarchical in SDC timing constraints
- The FPGA as an electronic component
- Using registers inside the input / output block
- Source-synchronous outputs
- Source-synchronous inputs
- Using 01-signal sampling with source-synchronous inputs
- Topics that are specific to FPGA vendors
- Topics that are specific to AMD FPGA (Xilinx)
- Vivado’s timing analysis on set_input_delay and set_output_delay constraints
- Vivado’s timing analysis on set_max_delay and set_min_delay
- Vivado: Finding the "maximal frequency" after synthesis
- Comparing Vivado's block design files
- Partial Reconfiguration with Vivado: Main page
- Understanding Partial Reconfiguration with Vivado
- How-To on Partial Reconfiguration with Vivado
- Xilinx Partial Reconfiguration: Reset and decoupling
- Remote Update with Partial Reconfiguration on Vivado
- Using FIFOs on Versal APAC FPGAs
- Topics that are specific to Intel FPGA (Altera)
- Quartus’ timing analysis on set_input_delay and set_output_delay constraints
- Quartus, timing closure: Obtaining a concise multi-corner timing path report
- Quartus: The importance of derive_pll_clocks in the SDC file
- Quartus / Linux: Programming the FPGA with command-line
- Quartus: Packing registers into I/O cells
- General topics
- The Golden Rules for proper FPGA design
- Electronic Exorcism: Why FPGAs sometimes behave as if they are possessed
- Index for pages about Xillybus
- Quick start guide to Xillybus
- The "Hello, world" test with Xillybus on Linux
- The "Hello, world" test with Xillybus on Windows
- Quick start guide to custom Xillybus IP cores
- Simple data acquisition with Xillybus
- Accessing Xillybus' device files
- Other topics
- Resetting a USB device on Linux (and maybe control its power supply)
- Conversion between Galois and Fibonacci polynomials of Linear-Feedback Shift Register
- Index page for pages about Xillinux and Smart Zynq