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Vivado’s timing analysis on set_max_delay and set_min_delay

OK, what’s this?

This page is the example part of another post, which explains the meaning of set_max_delay and set_min_delay when used as I/O timing constraints.

The Verilog code that was used in these examples:

module top(
    input test_clk,
    input test_in,
(* IOB = "TRUE" *) output reg test_out
);

(* IOB = "TRUE" *) reg test_samp;

   always @(posedge test_clk)
     begin
	test_samp <= test_in;
	test_out <= test_samp;
     end
endmodule

The implementation was run for a Kintex Ultrascale.

The timing reports for the output port

In accordance with that other post, the timing constraints behind the examples below are:

create_clock -name theclk -period 20 [get_ports test_clk]
set_max_delay -to [get_ports test_out] 7
set_min_delay -to [get_ports test_out] 0
set_max_delay -from [get_ports test_in] 1
set_min_delay -from [get_ports test_in] -3

The timing report for the output port in response to set_max_delay:

Slack (MET) :             1.260ns  (required time - arrival time)
  Source:                 test_out_reg/C
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            test_out
  Path Group:             **default**
  Path Type:              Max at Slow Process Corner
  Requirement:            7.000ns  (MaxDelay Path 7.000ns)
  Data Path Delay:        2.626ns  (logic 2.201ns (83.817%)  route 0.425ns (16.183%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           0.000ns
  Clock Path Skew:        -3.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns
    Source Clock Delay      (SCD):    3.114ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Net Delay (Source):      1.282ns (routing 0.002ns, distribution 1.280ns)
  Timing Exception:       MaxDelay Path 7.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock theclk rise edge)     0.000     0.000 r  
    AG12                                              0.000     0.000 r  test_clk (IN)
                         net (fo=0)                   0.000     0.000    test_clk_IBUF_inst/I
    AG12                 INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.738     0.738 r  test_clk_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.105     0.843    test_clk_IBUF_inst/OUT
    AG12                 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.049     0.892 r  test_clk_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.839     1.731    test_clk_IBUF
    BUFGCE_X1Y0          BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.101     1.832 r  test_clk_IBUF_BUFG_inst/O
    X2Y0 (CLOCK_ROOT)    net (fo=2, routed)           1.282     3.114    test_clk_IBUF_BUFG
    BITSLICE_RX_TX_X1Y50 FDRE                                         r  test_out_reg/C
  -------------------------------------------------------------------    -------------------
    BITSLICE_RX_TX_X1Y50 FDRE (Prop_OUT_FF_BITSLICE_COMPONENT_RX_TX_C_Q)
                                                      0.734     3.848 r  test_out_reg/Q
                         net (fo=1, routed)           0.425     4.273    test_out_OBUF
    AL8                  OBUF (Prop_OUTBUF_HRIO_I_O)
                                                      1.467     5.740 r  test_out_OBUF_inst/O
                         net (fo=0)                   0.000     5.740    test_out
    AL8                                                               r  test_out (OUT)
  -------------------------------------------------------------------    -------------------

                         max delay                    7.000     7.000    
                         clock pessimism              0.000     7.000    
                         output delay                -0.000     7.000    
  -------------------------------------------------------------------
                         required time                          7.000    
                         arrival time                          -5.740    
  -------------------------------------------------------------------
                         slack                                  1.260

As already explained, this is a calculation of clock-to-output from the clock pin to the output pin.

The timing report for the output port in response to set_min_delay:

Slack (MET) :             2.242ns  (arrival time - required time)
  Source:                 test_out_reg/C
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            test_out
  Path Group:             **default**
  Path Type:              Min at Fast Process Corner
  Requirement:            0.000ns  (MinDelay Path 0.000ns)
  Data Path Delay:        1.009ns  (logic 0.848ns (84.050%)  route 0.161ns (15.950%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           0.000ns
  Clock Path Skew:        -1.233ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    0.000ns
    Source Clock Delay      (SCD):    1.233ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Source):      0.477ns (routing 0.002ns, distribution 0.475ns)
  Timing Exception:       MinDelay Path 0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock theclk rise edge)     0.000     0.000 r  
    AG12                                              0.000     0.000 r  test_clk (IN)
                         net (fo=0)                   0.000     0.000    test_clk_IBUF_inst/I
    AG12                 INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.339     0.339 r  test_clk_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.025     0.364    test_clk_IBUF_inst/OUT
    AG12                 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.015     0.379 r  test_clk_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.350     0.729    test_clk_IBUF
    BUFGCE_X1Y0          BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     0.756 r  test_clk_IBUF_BUFG_inst/O
    X2Y0 (CLOCK_ROOT)    net (fo=2, routed)           0.477     1.233    test_clk_IBUF_BUFG
    BITSLICE_RX_TX_X1Y50 FDRE                                         r  test_out_reg/C
  -------------------------------------------------------------------    -------------------
    BITSLICE_RX_TX_X1Y50 FDRE (Prop_OUT_FF_BITSLICE_COMPONENT_RX_TX_C_Q)
                                                      0.264     1.497 r  test_out_reg/Q
                         net (fo=1, routed)           0.161     1.658    test_out_OBUF
    AL8                  OBUF (Prop_OUTBUF_HRIO_I_O)
                                                      0.584     2.242 r  test_out_OBUF_inst/O
                         net (fo=0)                   0.000     2.242    test_out
    AL8                                                               r  test_out (OUT)
  -------------------------------------------------------------------    -------------------

                         min delay                    0.000     0.000    
                         clock pessimism              0.000     0.000    
                         output delay                -0.000     0.000    
  -------------------------------------------------------------------
                         required time                         -0.000    
                         arrival time                           2.242    
  -------------------------------------------------------------------
                         slack                                  2.242

In essence, this is the same calculation. The difference is that the minimal delays are taken into account for each logic element. And also, the requirement is 0 ns.

The timing reports for the input port

The timing report for the input port in response to set_max_delay:

Slack (MET) :             1.317ns  (required time - arrival time)
  Source:                 test_in
                            (input port)
  Destination:            test_samp_reg/D
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             theclk
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            1.000ns  (MaxDelay Path 1.000ns)
  Data Path Delay:        0.851ns  (logic 0.686ns (80.600%)  route 0.165ns (19.400%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        1.217ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.217ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.461ns (routing 0.002ns, distribution 0.459ns)
  Timing Exception:       MaxDelay Path 1.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AK8                                               0.000     0.000 r  test_in (IN)
                         net (fo=0)                   0.000     0.000    test_in_IBUF_inst/I
    AK8                  INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.664     0.664 r  test_in_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.042     0.706    test_in_IBUF_inst/OUT
    AK8                  IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.022     0.728 r  test_in_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.123     0.851    test_in_IBUF
    BITSLICE_RX_TX_X1Y49 FDRE                                         r  test_samp_reg/D
  -------------------------------------------------------------------    -------------------

                         max delay                    1.000     1.000    
    AG12                                              0.000     1.000 r  test_clk (IN)
                         net (fo=0)                   0.000     1.000    test_clk_IBUF_inst/I
    AG12                 INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.339     1.339 r  test_clk_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.025     1.364    test_clk_IBUF_inst/OUT
    AG12                 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.015     1.379 r  test_clk_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.350     1.729    test_clk_IBUF
    BUFGCE_X1Y0          BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.027     1.756 r  test_clk_IBUF_BUFG_inst/O
    X2Y0 (CLOCK_ROOT)    net (fo=2, routed)           0.461     2.217    test_clk_IBUF_BUFG
    BITSLICE_RX_TX_X1Y49 FDRE                                         r  test_samp_reg/C
                         clock pessimism              0.000     2.217    
                         clock uncertainty           -0.025     2.192    
    BITSLICE_RX_TX_X1Y49 FDRE (Setup_IN_FF_BITSLICE_COMPONENT_RX_TX_C_D)
                                                     -0.024     2.168    test_samp_reg
  -------------------------------------------------------------------
                         required time                          2.168    
                         arrival time                          -0.851    
  -------------------------------------------------------------------
                         slack                                  1.317

As already mentioned, there's no intuitive explanation to this calculation. Neither is there much to say about the timing report for the input port in response to set_min_delay:

Slack (MET) :             0.700ns  (arrival time - required time)
  Source:                 test_in
                            (input port)
  Destination:            test_samp_reg/D
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             theclk
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            -3.000ns  (MinDelay Path -3.000ns)
  Data Path Delay:        0.850ns  (logic 0.617ns (72.583%)  route 0.233ns (27.417%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        3.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.245ns (routing 0.002ns, distribution 1.243ns)
  Timing Exception:       MinDelay Path -3.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AK8                                               0.000     0.000 r  test_in (IN)
                         net (fo=0)                   0.000     0.000    test_in_IBUF_inst/I
    AK8                  INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.583     0.583 r  test_in_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.066     0.649    test_in_IBUF_inst/OUT
    AK8                  IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.034     0.683 r  test_in_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.167     0.850    test_in_IBUF
    BITSLICE_RX_TX_X1Y49 FDRE                                         r  test_samp_reg/D
  -------------------------------------------------------------------    -------------------

                         min delay                   -3.000    -3.000    
    AG12                                              0.000    -3.000 r  test_clk (IN)
                         net (fo=0)                   0.000    -3.000    test_clk_IBUF_inst/I
    AG12                 INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.738    -2.262 r  test_clk_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.105    -2.157    test_clk_IBUF_inst/OUT
    AG12                 IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.049    -2.108 r  test_clk_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.839    -1.269    test_clk_IBUF
    BUFGCE_X1Y0          BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.101    -1.168 r  test_clk_IBUF_BUFG_inst/O
    X2Y0 (CLOCK_ROOT)    net (fo=2, routed)           1.245     0.077    test_clk_IBUF_BUFG
    BITSLICE_RX_TX_X1Y49 FDRE                                         r  test_samp_reg/C
                         clock pessimism              0.000     0.077    
                         clock uncertainty            0.025     0.102    
    BITSLICE_RX_TX_X1Y49 FDRE (Hold_IN_FF_BITSLICE_COMPONENT_RX_TX_C_D)
                                                      0.048     0.150    test_samp_reg
  -------------------------------------------------------------------
                         required time                         -0.150    
                         arrival time                           0.850    
  -------------------------------------------------------------------
                         slack                                  0.700     

The timing reports with -datapath_only

In accordance with that other post, the timing constraints behind the examples below are:

create_clock -name theclk -period 20 [get_ports test_clk]
set_max_delay -datapath_only -from [get_ports test_in] 2
set_max_delay -datapath_only -from [all_registers] \
   -to [get_ports test_out] 3

The timing report for the output port:

Slack (MET) :             0.374ns  (required time - arrival time)
  Source:                 test_out_reg/C
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Destination:            test_out
  Path Group:             **default**
  Path Type:              Max at Slow Process Corner
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        2.626ns  (logic 2.201ns (83.817%)  route 0.425ns (16.183%))
  Logic Levels:           1  (OBUF=1)
  Output Delay:           0.000ns
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    BITSLICE_RX_TX_X1Y50                              0.000     0.000 r  test_out_reg/C
    BITSLICE_RX_TX_X1Y50 FDRE (Prop_OUT_FF_BITSLICE_COMPONENT_RX_TX_C_Q)
                                                      0.734     0.734 r  test_out_reg/Q
                         net (fo=1, routed)           0.425     1.159    test_out_OBUF
    AL8                  OBUF (Prop_OUTBUF_HRIO_I_O)
                                                      1.467     2.626 r  test_out_OBUF_inst/O
                         net (fo=0)                   0.000     2.626    test_out
    AL8                                                               r  test_out (OUT)
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
                         output delay                -0.000     3.000    
  -------------------------------------------------------------------
                         required time                          3.000    
                         arrival time                          -2.626    
  -------------------------------------------------------------------
                         slack                                  0.374

The timing report for the input port:

Slack (MET) :             0.757ns  (required time - arrival time)
  Source:                 test_in
                            (input port)
  Destination:            test_samp_reg/D
                            (rising edge-triggered cell FDRE clocked by theclk  {rise@0.000ns fall@10.000ns period=20.000ns})
  Path Group:             theclk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.000ns  (MaxDelay Path 2.000ns)
  Data Path Delay:        1.136ns  (logic 0.856ns (75.342%)  route 0.280ns (24.658%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Timing Exception:       MaxDelay Path 2.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AK8                                               0.000     0.000 r  test_in (IN)
                         net (fo=0)                   0.000     0.000    test_in_IBUF_inst/I
    AK8                  INBUF (Prop_INBUF_HRIO_PAD_O)
                                                      0.807     0.807 r  test_in_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.105     0.912    test_in_IBUF_inst/OUT
    AK8                  IBUFCTRL (Prop_IBUFCTRL_HRIO_I_O)
                                                      0.049     0.961 r  test_in_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.175     1.136    test_in_IBUF
    BITSLICE_RX_TX_X1Y49 FDRE                                         r  test_samp_reg/D
  -------------------------------------------------------------------    -------------------

                         max delay                    2.000     2.000    
    BITSLICE_RX_TX_X1Y49 FDRE (Setup_IN_FF_BITSLICE_COMPONENT_RX_TX_C_D)
                                                     -0.107     1.893    test_samp_reg
  -------------------------------------------------------------------
                         required time                          1.893    
                         arrival time                          -1.136    
  -------------------------------------------------------------------
                         slack                                  0.757

These timing reports show how set_max_delay with datapath_only narrows down the calculation to the data path.

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