This is the main page for four tutorial posts on Partial Reconfiguration with Vivado 2020.2, and hence covers Xilinx' series-7 FPGAs and later.
Xilinx' user guide, UG909, is the authoritative resource for implementing projects with Partial Reconfiguration on Vivado. These posts should be read as a complementary to this document, and definitely not a substitute for it.
There is also another page, which shows how to submit partial bitstreams over a PCIe or USB 3.x link, with the help of the Xillybus IP core.
The first post of this tutorial explains how the whole thing works, regarding Vivado and the FPGA's reprogramming itself. The second post follows this up and outlines the procedure for implementing an FPGA project with Partial Reconfiguration.
The third post discusses what happens while the FPGA is being reconfigured, and how to ensure it resumes operation properly. The fourth and last post is intended for those who want to use Partial Reconfiguration as a Remote Update feature, offering possible solutions for Vivado's lack of natural support for this use case. To complete the picture, it also briefly explains how Vivado uses Out-of-Context (OOC) runs and Design CheckPoint (DCP) files to carry out the Partial Reconfiguration flow.
These four posts are: