This series of three pages discusses how logic that is clocked by different clocks interacts in an FPGA design. In some cases, when the clocks are related, there's little special attention needed. However when the clocks are unrelated, the story becomes more complicated.
This way or another, it's important that the FPGA design tools apply timings constraints in a way that reflects the actual clock relations and the way the logic treats these clocks.
All this is discussed in these three pages: