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Resets and initializing an FPGA

Initializing an FPGA, possibly with resets, is a necessity to ensure proper and reliable operation. Yet, this topic is often neglected and reduced to using Verilog / VHDL code patterns with the false belief that if there's a reset, and it's used the way everyone else does, it's probably fine.

This series of three pages is an attempt to outline the main considerations on this topic.

The first page explains why the common use of asynchronous resets works partially at best. Those not using asynchronous resets at all can safely skip it.

The second page discusses synchronous vs. asynchronous resets, as well as other options for initializing the logic.

The third page takes a more practical approach, and suggests a reset controller for bringing up the FPGA correctly after powerup as well as user requested reset.

So once again, these are the three pages, as links with their titles:

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