- Crossing clock domains
- Clock domains, related clocks and unrelated clocks
- Metastability and the basics of clock domain crossing
- Clock domain crossing with data
- Initializing an FPGA and resets
- Asynchronous resets on FPGA: Not as easy as many believe
- Resets on FPGA: Synchronous, asynchronous or not at all?
- The logic for starting off and resetting an FPGA properly
- Arithmetics in Verilog